//################################################################################
// MIT License
// Copyright (c) 2024 ZhangYihua
//
// Change Logs:
// Date           Author       Notes
// 2020-10-18     ZhangYihua   first version
//
// Description  : 
//################################################################################

module udata_aeq_file #(
parameter           FILE                    = "file.txt",   // file path and name
parameter           FORMAT                  = "%h",         // data format
parameter           DW                      = 16,           // data width
parameter           DLY_NUM                 = 0,            // delay number for file data
parameter           IGNORE_NUM              = 0,            // ignore head number
parameter           IGNORE_DIFF             = 1             // ignore different(<=IGNORE_DIFF) between DUT data and golden data
) ( 
input                                       rst_n,
input                                       clk,
input                                       cke,

output  tri1                                done,   // 1'b0: file uncompleted; 1'b1: file completed; support wire-and logic
input               [DW-1:0]                data    // data from DUT
);

//################################################################################
// define local varialbe and localparam
//################################################################################
wire                [DW-1:0]                gold_data;
wire                                        gold_vld;
integer                                     gold_cnt;
reg                                         err;

//################################################################################
// main
//################################################################################

file2data #(
        .FILE                           (FILE                           ),	// file path and name
        .FORMAT                         (FORMAT                         ),	// data format
        .DW                             (DW                             ),	// data width
        .DLY_NUM                        (DLY_NUM                        )	// delay number
) u_file2data ( 
        .rst_n                          (rst_n                          ),
        .clk                            (clk                            ),
        .cke                            (cke                            ),

        .done                           (done                           ),	// 1'b0: file uncompleted; 1'b1: file completed
        .data                           (gold_data                      )   // data converted from file
);

assign gold_vld = u_file2data.vld;
assign gold_cnt = u_file2data.cnt;

initial begin:CHK
    reg [DW-1:0] diff;

    @(posedge rst_n);

    repeat(IGNORE_NUM) begin
        @(posedge clk);
        while((cke&gold_vld)!=1'b1) begin
            @(posedge clk);
        end
    end

    while(done==1'b0) begin
        @(posedge clk);
        while((cke&gold_vld)!=1'b1) begin
            @(posedge clk);
        end

        diff = (data>=gold_data) ? data - gold_data :   // diff is unsigned
                                   gold_data - data ;
        if (diff>IGNORE_DIFF) begin
            err = 1'b1;
            $error("*******   number %d    ******", gold_cnt);
            $display("    data %h is from DUT;", data);
            $display("    data %h is from file %s;", gold_data, FILE);
            $display("difference %h is too big.", diff);
            $stop;
        end else
            err = 1'b0;
    end
end

//################################################################################
// ASSERTION
//################################################################################

`ifdef CBB_ASSERT_ON
// synopsys translate_off


// synopsys translate_on
`endif

endmodule
